M6 deep dive: A brilliant 2nm design held back by bandwidth
Macworld
Our own review of the new Mac mini analyzed the performance and value of the M5 Pro version, but that chip has been around since the spring. Far more interesting is the M6, a new-generation processor made on TSMC’s 2nm process and sporting some interesting architectural changes. Our German sister site Macwelt reviewed that model, and found it to be a big jump over the preview Mac mini, which came equipped with an M4.
Now that the chip has been out for a couple of weeks, we’re starting to get some good technical breakdowns that discuss the finer architectural details of the chip. (Two of our favorites are Geekerwan and High Yield / SemiAnalysis.) They paint the picture of a processor with an interesting set of new advancements, primarily the result of TSMC’s new 2nm process and the increased density it enables. Here are some of the things we learned.
What 2nm enables
Along with the A20 Pro in the iPhone 18 Pro and iPhone Duo, the M6 represents the first of Apple’s chips to use the new 2nm manufacturing process from TSMC, and it’s one of the first mass-market 2nm chips in the world.
New manufacturing process technologies can be tricky to understand, but in essence, this new 2nm process has smaller features—gates and transistors and resistors and such—which means the same logic and RAM storage can fit into a smaller area. You can use this to make a smaller chip, or just to fit more chip “stuff” in the same area.
In the case of the M6, it allows Apple to increase core counts and add features while actually making the chip slightly smaller than the M5. The M6 is estimated to be about 142 mm2, compared to the M5’s 157 mm2. In fact, with the exception of the 119 mm2 M1, the M6 is the smallest M-series chip yet.
Despite increasing core counts and cache sizes, the M6 is slightly smaller than the M5, thanks to TSMC’s 2nm process.SemiAnalysis
This new manufacturing process brings more than just smaller, denser chip features. It also gives us a new type of transistor, GAAFET (gate-all-around field-effect transistor), which replaces the older FinFET design. It surrounds the gate material on all four sides, vs. just three sides as in the FinFET technology. It reduces leakage and makes the chips more electrically stable, so they can run at lower power and higher clock speeds.
Big CPU changes
With the M5, Apple rebranded its performance cores as “super cores.” In the M5 Pro and Max, the company used both the new super cores and new mid-range performance cores. Some chips, such as the A18 Pro, included both super and efficiency cores.
The M6 is the first Apple processor to use three different CPU core designs: 2 Super cores, 4 Performance cores, and 6 Efficiency cores. It’s not the first company to do this sort of thing, as Intel’s Panther Lake generation includes a 4-8-4 design with what it calls performance cores, efficiency cores, and low-power efficiency cores.
This new middle-child performance core is about half the size of a super core, and while not as fast, it’s a lot more powerful than the efficiency cores. So in essence, Apple took the four super and six efficiency CPU-core setup of the M5, and traded out two of the super cores for four Performance cores. It’s a good design, as it improves multi-core CPU performance greatly while not having a big impact on CPU die area or single-thread performance.
Foundry
The cache setup is similar to the M5 in many ways. The SLC (system-level cache, shared by all of the SoC’s components) is still 16 megabytes. The L2 cache has gone up to 20MB from 16MB in the M5, and it’s shared by the super cores and performance cores. Since it is now being used by six CPU cores instead of four, an equal increase in size makes sense. As with the M5, the super cores are weird in that they also have their own individual 1.5MB L2 caches in addition to the big shared L2.
The efficiency cores are said to be identical to those in the A20 Pro, and they’re quite capable in their own right, but they have their own separate L2 cache and AMX unit (a CPU complex dedicated to speeding up matrix math operations).
This is one of the biggest fundamental changes in the M6—a new three-tier CPU core setup, with S-cores that are more powerful and clocked higher than those in earlier processors. We’ll probably see this three-tier setup in the M7 as well.
A GPU starved for bandwidth?
Apple added two more GPU cores in the M6 compared to the M5, taking it from 10 cores to 12. This alone accounts for a 20 percent increase in peak GPU compute performance, but it’s also clocked slightly higher. The new core design does have faster geometry processing rates (important for 3D graphics scenes with complex geometry), but it’s mostly this core count and clock speed boost that is responsible for the better performance.
In real-world applications, we can’t help but think the GPU is limited by memory bandwidth. The M6 has a max memory bandwidth of 170 GB/sec, but only in the 24GB and 32GB models, which have LPDDR 5x RAM at 10,667 MT/sec. The 16GB model has slower memory running at 9,600 MT/sec, giving it the same 153 GB/sec as the M5.
That’s not a very big increase in memory bandwidth, especially when you consider it’s being shared with the CPU cores and Neural Engine.
Foundry
Despite a very modest increase in memory bandwidth, the increase in GPU cores and clock speeds helps the M6 improve 3D graphics performance by 20 percent or more. We’re left wondering: How much faster would it be with more memory bandwidth available?
If you’re going to add CPU cores, double Neural Engine cores, and add 25% more GPU cores while only increasing memory bandwidth by 10%, you would expect to be limited by memory bandwidth at almost every turn. The M6 has plenty of cache, but the A20 Pro just goes to show how much performance you can get from a wider memory bus, and it’s time for Apple to do the same for the base M-series chips as well.
Double Neural Engine
Speaking of memory-hungry operations, the M6 has the same doubled-up Neural Engine as the A20 Pro. It’s technically two separate 16-core Neural Engine units rather than a single 32-core one. Each 16-core cluster has its own separate cache that isn’t shared with the other, but there’s a single control unit for the entire array.
Foundry
It’s hard to know if this 16/16 split affects real-world performance more than just having a big 32-core Neural Engine with a single cache that’s twice as big, but we do see some nice performance gains, with the M6 running quantized models on the Neural Engine about 50 percent faster than the M4, and even 20 percent faster than the M5 Pro despite having a lot less memory bandwidth.
Still, it’s important to recognize that twice the cores does not equal twice the performance, especially if the system is limited in some other way. Again, we have to wonder if memory bandwidth is holding things back here.
M7 has one job: a wider memory bus
If the most recent rumors are to be believed, the M6 will be the only chip in this generation. We would typically either have an M6 Pro already, or get it in the spring of 2027, along with an M6 Max and even potentially an M6 Ultra. Then, Apple would start the next generation with the M7 in the fall of 2027.
Instead, so the rumors go, the M7 is being pulled in and will ship in the spring, with the M7 Pro/Max variants in the fall. This would leave the M6 as the sole chip in this generation.
Apple is said to be doing this primarily to accelerate the roadmap of its chips’ AI performance, and it’s easy to see why. The M6 has a 128-bit memory interface, the same as every base M-series chip since the M1. The only thing improving memory bandwidth is faster DRAM chips.
AI tasks, whether they are performed by the Neural Engine or the GPU, tend to be very memory intensive. We’ve seen how much the A20 Pro’s performance benefitted from increasing the memory bus by 50 percent from 64-bit to 96-bit, and it’s definitely time for the M series to do the same.
Yes, we expect architectural advancements in the CPU, GPU, and Neural Engine cores of the M7, but no single change would be as significant as increasing the memory bus to 192-bit or 256-bit. This would increase memory bandwidth to 255 GB/sec or 341 GB/sec with the same LPDDR5x memory and make graphics, GPU compute, and intensive AI tasks just fly.
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