Samsung Electronics presents next-generation 3D memory concepts at Future of Memory and Storage (FMS) 2026 in California, displaying mockups of two new architectures: zHBM and zNAND-O. Samsung’s memory leadership introduces the designs during a keynote and shows the models at its booth.
Samsung describes zHBM as a way to improve data transfer for AI accelerators by reducing the distance between logic processors and high-bandwidth memory. In conventional designs, HBM sits beside logic chips; Samsung instead stacks memory directly on top of the processor to increase bandwidth and improve power efficiency. The company says it supports the architecture using advanced bonding and integration techniques, including hybrid copper bonding and multiwafer bonding, to speed signal transfer and reduce thermal resistance.
Alongside zHBM, Samsung also previews zNAND-O, a separate 3D memory structure. One outlet additionally notes Samsung’s presentation includes references to a high-layer-count V10 BV-NAND concept with more than 400 layers, positioned as another approach to address data bottlenecks for AI workloads. Both sources frame the announcements as targeting performance and efficiency limits in AI systems.
